1. Field of the Invention
This invention relates to a method and circuit for actively controlling the impedance along the lines of a multiplex communication circuit, and more specifically for reducing the effective resistance and resulting time constant at a multiplex node in order to improve response time and increase digital transmission speeds (Kbps).
2. Description of the Prior Art
A vehicle-wide network multiplex communication system based upon the Society of Automotive Engineers (SAE) J1850 standard, which is incorporated herein by reference, may be optimized for providing communications for a variety of applications within automotive vehicles. Examples of these applications include low-speed body electrical signals, and medium speed data communication signals between control computers and between control computers and displays. One preferred embodiment of the J1850 standard operates at 41.67 Kbps. The physical layer is implemented as a multiplex wiring system, as illustrated in FIG. 1, composed of a variety of modules connected together by two twisted wires for communicating with differential pulse width modulation signals. Other modulation and digital encoding schemes such as NRZ (nonreturn to zero) may also be used in conjunction with this invention. The two wire differential twisted pair is preferred because of its high degree of immunity to electromagnetic noise.
Signals are transmitted differentially, with the signal on one line being the complement of the signal on the other line. The digital messages are encoded in a series of states consisting of a dominant or active state, which may be either a positive voltage or a negative voltage depending upon the polarity and signal protocol, and a recessive or passive state where the line voltage is established by the termination resistors. FIG. 2 illustrates a preferred pulse width modulation protocol for digitally encoded 0 and 1 bits according to one implementation of SAE J1850.
As the need for real-time information exchange among the various computers and control systems of the automotive vehicle increases, it is desirable to increase the speed from 41.67 Kbps to speeds such as 167 Kbps, 333 Kbps and 1,000 Kbps. In the SAE J1850 standard protocol, the most critical event occurs during the acknowledgement procedure whereby one node acknowledges to the originating node that a message has been received. The multiplex system must be able to arbitrate acknowledgements between two message recipients whose transmitted acknowledgements are separated by a time delay. The time delay allowed before arbitration fails is defined as the maximum allowable delay for a signal traveling within the system. This maximum allowable time delay is inversely proportional to the data rates of the digital signals. Therefore, in order to operate at higher data rates, the total time delay must be minimized to the extent possible.
The one way time delay for message transmission is made up of the following elements: (1) the propagation delay along the transmission line, (2) the propagation delay of the line driver, (3) the RC time constant of the receiver input filter, and (4) the combined RC time constant of the transmission line and nodes. The RC time constant of the receiver input filter is determined by the level of filtering desired for anti-aliasing. As the speed of the multiplex system is increased, the time constant must be reduced proportionately.
The combined RC time constant of the multiplex communication lines and the nodes is determined by the total length of the transmission line, the total number of nodes in the system, and the value of the terminator resistors. For a 40 meter system with 32 nodes, each having a capacitance of 250 pf from each line to ground and line capacitances of 67.5 pf/m between lines and 40 pf between line and ground, and terminator resistors equal to 90 ohms, the RC time constant is approximately 1.1 microseconds which corresponds to about 650 nsec in signal delay. Any possible reduction in the delay due to the RC time constant has a significant effect on increasing the maximum operating speed of the system because it represents nearly half of the total system delay.
The maximum allowable time delay is equal to the sum of the delay of the message from the sender to the receiver, plus the delay of the acknowledgement from the receiver to the sender. In order to determine the maximum allowable delay, the line RC time constant delay must be added with the other delay factors described above. The maximum delay occurs when the delay between two acknowledging messages is large enough to cause the trailing edge of the first phase of one message to be sampled during the second phase of the other message or the second phase being sampled during the third phase, such that an incorrect acknowledgement occurs in the former case and an error condition occurs in the latter case.
The signal waveform illustrating the effect introduced on the square waveform by the slow RC time constant is shown in trace B of FIG. 6. Trace A of FIG. 6 illustrates the desired waveform that will be produced by the variable impedance reduction controlled by the preferred embodiment of the present invention.
Therefore, a first object of the present invention is to dynamically reduce the effective resistance at each node of the multiplex system in order to decrease the RC time constant during the signal transition for allowing a more rapid slew of the signal from one logic state to another. Another object is that the active circuitry utilized for the impedance reduction must be inactive outside of a transition band between the two basic states so as to not change the termination resistance when the signal is in either the full active (dominant) or passive (recessive) state.